【英伟达NVIDIA】上海研发中心招聘芯片设计工程师

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【英伟达NVIDIA】上海研发中心招聘芯片设计工程师
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nvidia 等级 ☆

楼主发表于 2017/12/24 23:42:56 编辑

职位□□: 技术领先，成长空间大，年终奖金，五险一金
工作地址：上海浦东新区秋月路26号
简历投递邮箱：heatherl@nvidia.com，简历请以附件形式发送

Physical Design CAD Engineer
岗位职责：
Develop the physical design flow and methodology for all chips in NVIDIA (including GeForce®/Tegra™/Tesla™/Quadro™).
Work with EDA vendors on tools evaluation and improvement.
Develop inhouse tools and solutions.
Support the global physical design team.

要求：
电子/通信/计算机相关专业本科及以上学历
具备任一领域专业经验：Floorplan, Place & Route, STA, layout DRC/LVS, DFT, circuit design, RTL.
编程能力强
加分项：
熟悉Perl/TCL/Shell等脚本语言
具有超大规模集成电路设计开发经验
了解EDA工具： (ICC/DC/PT/STAR-RC/Astro/PC/Talus), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) 等

ASIC Physical Design Engineer
岗位职责：
Chip integration and netlist generation
Synthesis
Netlist quality check
Formal Verification
Constraints creation and validation, timing budget.
Co-work with PR engineers to implement chip partition and floorplan
Work in conjunction with RR engineers to achieve timing closure for both partition and full chip level
Achieve special timing closure, such as io, test, clock etc.
Function eco creation
Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
Flow automation development
Methodology in any of above areas.

要求：
电子/通信/计算机相关专业本科及以上学历
具备IC设计项目经验
了解circuit design, digital design
熟悉EDA 软件：Synopsys (DC/PT/Formality), Cadence (LEC)
加分项：
熟悉Perl/TCL等脚本语言
英文能力强

Senior ASIC Design Verification Engineer
岗位职责：
You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality state of the art products.
Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
You responses to build block/IP testbench based on UVM methodology.
The responsibilities includes building test run and regression flow. Triage failures in regression and help designer root cause the bug.
Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
Take SOC verification on fullchip test environment for IPs
Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
Deploy the advanced verification methodology and infrastructure of the SOC/IP

要求：
电子/通信/计算机相关专业本科及以上学历
硕士3年以上行业经验，本科5年以上行业经验
熟悉UVM/VMM/OVM等验证方法，工具及流程
熟悉验证流程，包括testplan, test, coverage model, testbench, BFM modeling.
对Verilog and HVL语言有深入理解
加分项：
掌握Perl ，C或C++ 语言
有架构/设计相关经验
掌握以下任一脚本语言 Shell, Ruby, Python
良好的交流能力，分析能力和团队合作能力

ASIC Design/Verification Engineer
岗位职责：
Micro-architecture definition for System-level modules (Reset, Fuse, Strap, In-silicon measurement, Floorsweep, etc…)
RTL design, synthesis, timing and silicon bring-up
Unit-level and System-level verification
Chip level integration

要求：
电子/通信/计算机相关专业本科及以上学历
熟悉验证方法，工具及流程
熟悉ASIC前端包括： RTL design, synthesis，timing analysis
加分项：
具备以下知识背景：Video techniques, SOC architecture and Computer architecture
掌握Perl ，C或C++ 语言
良好的交流能力，分析能力和团队合作能力

ASIC Verification Engineer (Clocks)
岗位职责：
Module-level or Chip-level logic design, synthesis, timing constraints, and silicon bring-up.
Module-level or Chip-level verification, both for function and test mode
Methodology or Flow development for above tasks.

要求：
电子/通信/计算机相关专业本科及以上学历
熟悉ASIC设计/验证
熟悉ASIC设计/验证语言：C/C++, Verilog or VHDL
了解Perl/Python/TCL/Ruby等脚本语言
良好的交流能力，分析能力和团队合作能力
加分项：
了解JTAG/DFT/OCC

ASIC SOC Design Engineer
岗位职责：
In this position, you will have the opportunity to be responsible for creating complex GPUs and SOCs and interface directly with unit-level, Physical Design, CAD, Package Design, Software, DFT and other teams. Additionally, you will be involved with defining and creating methodologies that create more efficient and flexible SOCs in future.

要求：
电子/通信/计算机相关专业本科及以上学历
掌握Perl等其他脚本语言
熟悉ASIC设计/验证流程
良好的交流能力，分析能力和团队合作能力
加分项：
了解System-On-Chip
了解 RTL 设计

ASIC SOC Methodology Engineer
岗位职责：
Be responsible for all aspects of the padring methodology work which includes maintaining existing padring RTL generation flow
Providing support to the padring designers and DFT team, and owning the creation, implementation, and verification of the next-generation padring generation flow
Interfacing with cross functional teams, such as: Physical Design, CAD, Package Design, DFT SOC Design System/Platform architecture, library memory and IO teams to understand the padring design

要求：
电子/通信/计算机相关专业本科及以上学历
掌握Perl/TCL/C/C++
熟悉ASIC设计/验证流程
具备DFT知识JTAG/BDSL/IEEE1500
良好的交流能力，分析能力和团队合作能力
加分项：
具有以下经验floor planning，board level
了解System-On-Chip
了解 RTL 设计

ASIC Power Engineer
岗位职责：
Create a methodology/algorithm to evaluate power efficiency on high-level (architecture) designs.
Support IP designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch (ASIC) level.
Understand and perform block level and chip-level power analysis.
Communicate/Cooperate with local and abroad teams with power-related projects.
Co-work with power ARCH team/IP team to evaluate new low-power technologies and improve chip power efficiency.

要求：
电子/通信/计算机相关专业本科及以上学历
熟悉ASIC设计/验证流程
掌握C/C++ ，Perl/Python等脚本语言
良好的交流能力，分析能力和团队合作能力

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