2018西部数据校园招聘

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2018西部数据校园招聘
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51poiu 等级 ★★★★

楼主发表于 2017/9/25 1:12:01 编辑

2018西部数据校园招聘
工作地点：上海【面向2018届&2017届毕业生招募】
—— 晟碟半导体（上海）有限公司
西部数据介绍
Digital Corporation (NASDAQ：WDC) 西部数据公司是业内领先的存储技术和解决方案提供商，能让用户创建、管理、体验和保存数据。西部数据提供种类齐全且极具吸引力的高质量存储解决方案，它们具有以客户为中心的创新性以及极高的效率、灵活性和存储速度，可满足不断变化的市场需求。产品以 HGST、SanDisk 和 WD 品牌销售给 OEM、分销商、经销商、云基础架构提供商和消费者。如需了解更多西部数据相关资讯，请访问西部数据的官方网站https://www.wdc.com 。
SanDisk闪迪是西部数据的一个品牌。愈27年来，闪迪不断扩展存储的可能性，即便在最具挑战性的环境中，闪迪都能确保数据随时可靠可用，让企业和消费者安然无忧。我们的产品应用于世界领先的数据中心，嵌入各种变革性的智能手机、平板电脑和笔记本电脑中，更备受全球消费者的信赖。作为一家纵向整合的存储公司，我们能够减少从研发到产品实现的时间，迅速交付创新且优质的解决方案。从掌上电脑到超大规模数据中心，闪迪存储解决方案创造无限可能。
SanDisk 闪迪于2005年开始在上海紫竹科技园设立封装测试工厂— 晟碟半导体（上海）有限公司（以下简称“晟碟”）。晟碟是由SanDisk独资在上海设立的第一个封测厂，地址在闵行区紫竹园区江川东路388号，注册资金为22900万美元，投资总额为68700万美元，晟碟专门为晟碟半导体（上海）有限公司及其关联公司晟碟信息科技（上海）公司、闪迪贸易 (上海) 有限公司、闪迪贸易（上海）有限公司北京分公司、昇达香港有限公司深圳代表处提供闪存产品的封装、测试服务并从事产品封装、测试技术的研发。作为业内领先的闪存产品封装和测试厂，晟碟目前的封装测试产能已经达到每天超过250万个芯片，主要的产品类型为闪存卡（Flash Memory Card）及嵌入式闪存模块（Embedded Flash Memory Module）。晟碟生产的产品销往世界各地。更多信息请访问www.sandisk.cn 。

校园宣讲安排：
招募流程：
网申&在线测评——校园宣讲——笔试/面试——录用通知——加入西数

网申时间:

网申地址:

宣讲会安排：

地点学校时间地点
上海上海大学 10月9日周一18:30-20:30 乐乎新楼2号楼学海厅
杭州浙江大学 10月29日周日15:00-17:00 永谦活动中心报告厅1
南京东南大学 10月23日周一18:30-20:30 榴园宾馆新华厅
成都中国电子科技大学 9月25日周一19:00-21:00 学生活动中心NEC厅（沙河校区）
西安西安电子科技大学 10月15日周日19:00-21:00 阶教101
上海上海交通大学 10月25日周三16:00-18:00 铁生馆200号
宁波诺丁汉大学 10月18日周三18:30-20:30 D8-C06
上海复旦大学 11月1日周三18:30-20:30 光华楼东辅楼103
SanDisk 开放日 11月9日周四全天上海市闵行区江川东路388号

宣讲会现场有好礼相送！
西数更多招募活动，晶彩待续

申请职位列表【面向2018届&2017届毕业生招募】
R&D（研发）
Senior Engineer, Reliability Engineering 高级可靠性测试工程师
Senior Engineer, Analytical & Characterization Engineering 高级特征性测试分析工程师（芯片验证方向）
Senior Engineer, Design Verification(MT) 高级设计验证工程师
Senior Engineer, Test Engineering(ST) 高级系统软件工程师
Senior Engineer, Product Design Engineering 高级产品设计工程师
Senior Engineer, Product Design Engineering 高级产品设计工程师（产品测试方向）
Senior Engineer, Product Design Engineering 高级产品设计工程师（固态硬盘）
Senior Engineer, Product Design Engineering 高级产品设计工程师（闪存研发）
Senior Engineer, Product Design Engineering 高级产品设计工程师（固件测试方向）
Senior Engineer, Packaging Engineering 高级封装研发工程师（新产品制程工程）
Senior Engineer, Packaging Engineering 高级封装研发工程师（先进封装研发）
Senior Engineer, Packaging Engineering 高级封装研发工程师（标杆管理）
Senior Engineer, Packaging Engineering 高级封装研发工程师（核心工程—先进芯片堆叠研发）
Senior Engineer, Packaging Engineering 高级封装研发工程师（核心工程—先进封装设备研发）
Operation（生产运营）
Senior Engineer, Test Engineering(SSD) 高级测试工程师（固态硬盘）

1. Senior Engineer, Reliability Engineering高级可靠性测试工程师
Responsibilities:
Develop Memory Reliability Specifications
Develop reliability Characterization Plan
Develop Memory Qualification Plan
Execute Characterization and Qualification
Perform failure analysis, tracing root cause and corrective actions
Develop reliability test scripts
Develop Data Analysis/Automation scripts compatible with Big Data
Specify/procure/bring up Rel Test/Debug/data analysis Equipment
Work with Fab/Device/Packaging/Design/Characterization/BUs/PETE/Quality to resolve issues
Requirements:
Master Degree in Microelectronics, Electronics/Electrical Engineering, Computer Science, with adequate knowledge on semiconductor packaging and testing process and technology.
NAND/NOR Flash memory knowledge is preferable
Good oral English and communication skills
Well understand reliability test mechanism and typical failure phenomenon
Well understand reliability test spec/procedure defined by JEDEC
Good programming skills: C++, Python, Big Data
Experience of text processing with python, Perl

2. Senior Engineer, Analytical & Characterization Engineering高级特征性测试分析工程师（芯片验证方向）
Responsibilities:
Test development and implementation for testing and characterization of NAND memory on ATE test systems.
In this role, the individual is responsible for all aspects of test debug and validation, correlation, revision control and test/handler setup.
Perform characterization of all memory technology and designs for logic/ functionality, performance, power consumption, timing and some aspects of reliability.
Work with corresponding teams for product issue resolution.
Write special tools to speed up the process of design debug and other activities such as memory qualification failure analysis and yield issue.
Customize test coverage and define new test strategy for specific customers.
Provide product and test engineering support for design debug activity and failure analysis. Silicon micro probing may be required.
Provide product-engineering support for solving production yield issues through improvement from design or packaging technology. Design and validate test screens as necessary.
Organize and monitor projects from inception through delivery. Maintain database of statistical data collection and analysis.
Requirements:
Require familiarity with common lab equipment such as digital scope, logic analyzer.
Strong skills of testing program development on ATE, solid skills on Language C++/C#
Require good written and verbal English.
Requires BS/MS degree or equivalent with engineering background.

3. Senior Engineer, Design Verification(MT) 高级设计验证工程师
Responsibilities:
In this position, the individual will assist in the debugging and development of NAND KGD, BI and MT test programs for FLASH automated test systems.
The ability to write correct, clean and well documented programs strictly according to design documents and data sheets.
Support and improve the full-automated test cell with tester and device handler, developing characterization and evaluation programs for new products and supporting failure analysis with product engineering.
The individual will also be responsible to co-work with various engineering departments to solve program and product issues.
When urgent needs arrive, the individual need to meet the deadline as required.

Requirements:
Bachelor or Master Degree in Electronic, Automation, Computer Science or related major Strong programming skills preferred in Java or C; excellent debugging and trouble shoorting skills
Proficiency in oscilloscopes, logic analyzers, and multi-meters is a plus.
Excellent English communication (written and verbal) and interpersonal skills
Ability to achieve results in a fast changing and demanding working environment.

4. Senior Engineer, Test Engineering(ST) 高级系统软件工程师

Responsibilities:
In this position, the individual will assist in the debugging and development of NAND KGD, BI and MT test programs for FLASH automated test systems.
The ability to write correct, clean and well documented programs strictly according to design documents and data sheets.
Support and improve the full-automated test cell with tester and device handler, developing characterization and evaluation programs for new products and supporting failure analysis with product engineering.
The individual will also be responsible to co-work with various engineering departments to solve program and product issues.
When urgent needs arrive, the individual need to meet the deadline as required.
Requirements:
Bachelor or Master Degree in Electronic, Automation, Computer Science or related major Strong programming skills preferred in Java or C; excellent debugging and trouble shoorting skills
Proficiency in oscilloscopes, logic analyzers, and multi-meters is a plus.
Excellent English communication (written and verbal) and interpersonal skills
Ability to achieve results in a fast changing and demanding working environment.

5. Senior Engineer, Product Design Engineering高级产品设计工程师
Responsibilities:
BS or higher in Electrical Engineering, Computer Engineering, Physics, Materials Science or other related technical field
Deep understanding on electrical failure analysis methodology.
Demonstrated ability to analyze problems, diagnose root cause, and apply corrective actions.
Excellent data analysis skills including data crunch, statistical analysis, and interpretation
Highly self-motivated, passionate about troubleshooting and solving complex problems
A basic understanding of system, F/W working principle, device physics is beneficial
Good English communication skill
Requirements:
Performing deep electrical failure analysis during new product development and ramping phase. Shoot failures from both wafer level and package level. Create analysis report based on FA finding and define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.)
Monitor memory health level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction.
Define the test flow, screen/stress method based on root cause analysis of failures. Work with TE to come up with detail plans and drive for implementation.

6. Senior Engineer, Product Design Engineering高级产品设计工程师（产品测试方向）
Responsibilities:
TBD
Requirements:
TBD
7. Senior Engineer, Product Design Engineering高级产品设计工程师（固态硬盘）
Responsibilities:
TBD
Requirements:
TBD
8. Senior Engineer, Product Design Engineering高级产品设计工程师（闪存研发）
Responsibilities:

TBD

Requirements:
TBD

9. Senior Engineer, Product Design Engineering高级产品设计工程师（固件测试方向）
Responsibilities:
Be responsible for development of testing FW for Nand flash memory and MCU and deliver high quality program with high efficiency.
Be responsible for Failure analysis, code/product/hardware issue debugging.
Working with other product line teams on screen development and RMA analysis.
Support manufacturing department on yield improvement and TTR (test time reduction) and still meet quality goals.
Innovatively make continuous improvement on test program/process and co-work with other departments effectively.
Requirements:
Electrical Engineering major with BS/MS degree and have background knowledge on MCU/FW/Nand is plus.
Familiar with PETE R&R. Have knowledge on Nand operation/failure mode/testing.
Familiar with C/Python, having experience with programming.
Ability to troubleshoot, analyze problems, multi-task and meet deadlines.
Excellent English communication (written and verbal) and interpersonal skills
Good team work, willing to learn, logical thinking and can work under pressure.

10. Senior Engineer, Packaging Engineering高级封装研发工程师（新产品制程工程）
Responsibilities:
Develops packaging assembly process for new product, and introduces new product into production.
Defines new product’s package & assembly process requirements to meet product and customer
Requirements:
Characterizes package material, tool and process and coordinate qualification programs for product quality/cost/productivity effectiveness.
Prepares and/or updates specifications for piece parts of integrated circuits or semiconductor assemblies
Acts as a liaison with vendors.
Requirements:
Master or PhD Degree with Major in Mechanical Engineering, Material Science, Polymer Science, or Electrical Engineering;
Good to have internship experience or knowledge on semiconductor packaging;
Good to have a strong interest in electronic gadgets;
Excellent English communication (written and verbal) and interpersonal skills;
Hard working, and be able to work under high pressure

11. Senior Engineer, Packaging Engineering高级封装研发工程师（先进封装研发）
Responsibilities:
Process development on Hybrid Flip Chip, interact Technology, Material & Equipment;
Interface of process, to communicate the requirement from inner/outer customers;
Recipe Baseline & design rule maintain;
Trouble shoot for Flip Chip process;
Program management for new/upgrade process;
New Package development, qualification till VM, involve thru process & technology.
Requirements:
Be capable of occasionally over time work and oversea business travel.
Master Degree and up;
Major in Material science / Semiconductor / Assembly engineering;
Skill of Static Analysis;
Good English communication (written and verbal) skills;
Able to do international travel occasionally;
Self-motivated, teamwork, hardworking, and be able to work under high pressure.

12. Senior Engineer, Packaging Engineering高级封装研发工程师（标杆管理）
Responsibilities:
PID Quality Control for new wafer technology:
Thin Die Qual design and validation;
PID Charz DOE design and validation;
PID process change related Charz DOE design and validation;
PID tape out involvement;
PID design with Lesson Learnt and FMEA;
PID PNTF, Statistic Design & Analysis, IVT, VECQ, ePPM Score card, Measurement Instruction, Validation, Toll Gate, etc.
New Technology Programs Design and Development Quality Assurance:
TDW/TDS/EDS/MDS, PNTF, CFMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, etc.
New PlatForms Design and Development Quality Assurance
Proposing, Verifying, Ground Rule, PNTF, PF-FMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, DI team, etc.
New Packages (retail) Design and Development Quality Assurance
PDS signature, Recipe Baseline, TDCN, IVT, Toll Gate, etc.
TDCN and DCCB review committee.
Excursion/Abnormal Control
RCA, Agile Team, DMAIC, etc.
Competitor Analysis for new Technology and PlatForm
Flip Chip, Fan In/Out, 3D NAND, High capacity PKG, etc.
Charz Analysis
FIB/SEM/EDX/3D X-ray/TEM/X-section/etc.
Requirements:
Master degree in Microelectronic science and technology or Material science and technology or Mechanical engineering or Electrical Engineering.
English communication skills: CET-6, be fluent both in oral and written English.
Basic understanding of assembly process flow & materials and wafer fabrication processes.
Basic knowledge of operation principle for NAND/DDR/ASIC.
Basic Computer & Microsoft Office skills are required, AutoCAD/Cadence/JMP are preferred.
Be capable of analyzing SEM/FIB/TEM/EDX results, operating is preferred.
Ability to achieve results in a fast moving, dynamic environment.
Ability to troubleshoot and analyze complex problems.
Ability to multi-task and meet deadlines with team work.
Open mind and positive communication with In-time feedback.
Good Adoptability and Agility with fast changing environment.
Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
A proven desire to work as a team member, both on the same team and cross team.
Willingly creative and exceed.
Excellent English communication (written and verbal) and interpersonal skills.
Be capable of occasionally over time work and oversea business travel.

13. Senior Engineer, Packaging Engineering高级封装研发工程师（核心工程—先进芯片堆叠研发）
Responsibilities:
Process development on Advanced Die Attach, interact Technology, Material & Equipment;
Interface of process, to communicate the requirement from inner/outer customers;
Recipe Baseline & design rule maintain;
Trouble shooting for Advanced Die Attach process;
Program management for new/upgrade process;
New Package development, qualification, LVM till HVM, involve through process & tec

51poiu 等级 ★★★★

2 楼发表于 2017/9/28 2:10:17 编辑

51poiu 等级 ★★★★

3 楼发表于 2017/10/10 3:02:47 编辑

SanDisk闪迪是西部数据的一个品牌。愈27年来，闪迪不断扩展存储的可能性，即便在最具挑战性的环境中，闪迪都能确保数据随时可靠可用，让企业和消费者安然无忧。我们的产品应用于世界领先的数据中心，嵌入各种变革性的智能手机、平板电脑和笔记本电脑中，更备受全球消费者的信赖。作为一家纵向整合的存储公司，我们能够减少从研发到产品实现的时间，迅速交付创新且优质的解决方案。从掌上电脑到超大规模数据中心，闪迪存储解决方案创造无限可能。

51poiu 等级 ★★★★

4 楼发表于 2017/10/14 11:30:26 编辑

SanDisk 闪迪于2005年开始在上海紫竹科技园设立封装测试工厂— 晟碟半导体（上海）有限公司（以下简称“晟碟”）。晟碟是由SanDisk独资在上海设立的第一个封测厂，地址在闵行区紫竹园区江川东路388号，注册资金为22900万美元，投资总额为68700万美元，晟碟专门为晟碟半导体（上海）有限公司及其关联公司晟碟信息科技（上海）公司、闪迪贸易 (上海) 有限公司、闪迪贸易（上海）有限公司北京分公司、昇达香港有限公司深圳代表处提供闪存产品的封装、测试服务并从事产品封装、测试技术的研发。作为业内领先的闪存产品封装和测试厂，晟碟目前的封装测试产能已经达到每天超过250万个芯片，主要的产品类型为闪存卡（Flash Memory Card）及嵌入式闪存模块（Embedded Flash Memory Module）。晟碟生产的产品销往世界各地。

51poiu 等级 ★★★★

5 楼发表于 2017/10/18 10:06:59 编辑

西部数据介绍
Digital Corporation (NASDAQ：WDC) 西部数据公司是业内领先的存储技术和解决方案提供商，能让用户创建、管理、体验和保存数据。西部数据提供种类齐全且极具吸引力的高质量存储解决方案，它们具有以客户为中心的创新性以及极高的效率、灵活性和存储速度，可满足不断变化的市场需求。产品以 HGST、SanDisk 和 WD 品牌销售给 OEM、分销商、经销商、云基础架构提供商和消费者。如需了解更多西部数据相关资讯，请访问西部数据的官方网站https://www .wdc.com 。
SanDisk闪迪是西部数据的一个品牌。愈27年来，闪迪不断扩展存储的可能性，即便在最具挑战性的环境中，闪迪都能确保数据随时可靠可用，让企业和消费者安然无忧。我们的产品应用于世界领先的数据中心，嵌入各种变革性的智能手机、平板电脑和笔记本电脑中，更备受全球消费者的信赖。作为一家纵向整合的存储公司，我们能够减少从研发到产品实现的时间，迅速交付创新且优质的解决方案。从掌上电脑到超大规模数据中心，闪迪存储解决方案创造无限可能。
SanDisk 闪迪于2005年开始在上海紫竹科技园设立封装测试工厂— 晟碟半导体（上海）有限公司（以下简称“晟碟”）。晟碟是由SanDisk独资在上海设立的第一个封测厂，地址在闵行区紫竹园区江川东路388号，注册资金为22900万美元，投资总额为68700万美元，晟碟专门为晟碟半导体（上海）有限公司及其关联公司晟碟信息科技（上海）公司、闪迪贸易 (上海) 有限公司、闪迪贸易（上海）有限公司北京分公司、昇达香港有限公司深圳代表处提供闪存产品的封装、测试服务并从事产品封装、测试技术的研发。作为业内领先的闪存产品封装和测试厂，晟碟目前的封装测试产能已经达到每天超过250万个芯片，主要的产品类型为闪存卡（Flash Memory Card）及嵌入式闪存模块（Embedded Flash Memory Module）。晟碟生产的产品销往世界各地。

51poiu 等级 ★★★★

6 楼发表于 2017/10/27 13:56:15 编辑

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